RoMoL 2016: Invited Speakers

The following distinguished scientists have already accepted to speak at RoMoL 2016.

Yale Patt

  • Yale N. Patt (U. of Texas at Austin): Yale Patt is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin, and holds the Ernest Cockrell, Jr. Centennial Chair in Engineering. He also holds the title of University Distinguished Teaching Professor. Prof. Patt was elected to the National Academy of Engineering in 2014, among the highest professional distinctions bestowed upon an engineer.

He earned his B.S. at Northeastern University and his M.S. and Ph.D. at Stanford University, all in electrical engineering. He has received a number of awards for his research and teaching, most notably the highest honor in his specialty computer architecture, the 1996 IEEE/ACM Eckert-Mauchly Award, “for important contributions to instruction level parallelism and superscalar processor design,” and the highest honor in computer science education, the 2000 ACM Karl V. Karlstrom Outstanding Educator Award. His research has spanned more than five decades, including WOS module (1966), HPS (starting in 1985), the two-level branch predictor (starting in 1991), SSMT (1999), ACMP (2007), Morphcore (2012), and the runahead buffer (2015).

He has co-authored (with his former PhD student Professor Sanjay Jeram Patel) “Introduction to Computing: from bits and gates to C and beyond” (McGraw-Hill 2000; 2e, 2004), a revolutionary approach to introducing serious students to computing. They are currently working on the 3rd edition.


Thomas Sterling

  • Thomas Sterling (Indiana University): Thomas Sterling holds the position of Professor of Informatics and Computing at the Indiana University (IU) School of Informatics and Computing Department of Intelligent Systems Engineering (ISE) as well as serves as Chief Scientist of the IU Center for Research in Extreme Scale Technologies (CREST). Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow, Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia.

Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work. He was the PI of the HTMT Project sponsored by NSF, DARPA, NSA, and NASA to explore advanced technologies and their implication for high-end computer system architectures. Other research projects included the DARPA DIVA PIM architecture project with USC-ISI, the Cray Cascade Petaflops architecture project sponsored by the DARPA HPCS Program, and the Gilgamesh high-density computing project at NASA JPL. Thomas Sterling is currently engaged in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding co-design for the development of future generation Exascale computing systems. ParalleX is currently the conceptual centerpiece of the XPRESS project as part of the DOE X-stack program and has been demonstrated in proof-of-concept in the HPX-5 runtime system software. Dr. Sterling is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS. He is also co-guest editor with Bill Gropp of the HPCwire Exascale Edition.


Burton Smith

  • Burton Smith (Microsoft): Burton J. Smith, Technical Fellow for Microsoft Corporation, works with various groups within the company to help address the challenges brought about by the emergence of many-core systems and the increasing importance of distributed services. Before joining Microsoft in December 2005 he co-founded Cray Inc., formerly Tera Computer Company, where he variously served as its chief scientist, a member of the board of directors, and its chairman until 1999. Before that, Smith spent six years with Denelcor, Inc. and three years at the Institute for Defense Analyses Supercomputing Research Center.

In 2003, Smith received the Seymour Cray Award from the IEEE Computer Society and was elected to the National Academy of Engineering. He received the Eckert-Mauchly Award in 1991 given jointly by IEEE and ACM and was elected a fellow of each organization in 1994. He was elected Fellow of the American Academy of Arts and Sciences in 2010. Smith attended the University of New Mexico, where he earned a BSEE degree, and the Massachusetts Institute of Technology, where he earned SM, EE, and Sc.D degrees.


Mateo Valero

  • Mateo Valero (Barcelona Supercomputing Centre/UPC): Mateo Valero is a full professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 600 papers, has served in the organization of more than 300 International Conferences and he has given more than 400 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

Dr. Valero has been honored with several awards. Among them, the Eckert-Mauchly Award, Seymour Cray Award, Harry Goode Award, ACM Distinguished service, Euro-Par Achievement Award, the “King Jaime I” in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria, Zaragoza, Complutense de Madrid, Cantabria and Granada in Spain and by the University of Veracruz in Mexico. “Hall of the Fame” member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008). Prof. Valero is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow. He is a correspondent academic of the Royal Spanish Academy of Sciences, and member of the Royal Spanish Academy of Engineering, the Royal Academy of Science and Arts, the Academia Europea, and the Mexican Academy of Science.


Per Stenstrom

  • Per Stenstrom (Chalmers University of Technology): Per Stenstrom is a professor of computer engineering at Chalmers University of Technology. His research interests are in parallel computer architecture. He has authored or co-authored four textbooks and more than 150 publications in this area. He is known for his many contributions to high-performance memory systems which has awarded him a Fellow of the ACM and the IEEE. He has extensive experience in scientific publishing as editor-in-chief and program chair of prestigious scientific journals and conferences. Apart from acting as the associate editor-in-chief of JPDC in the architecture area, he acts as senior associate editor of ACM TACO.

He has been program chair or co-chair of the IEEE/ACM Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, the IEEE Parallel and Distributed Processing Symposium and ACM International Conference on Supercomputing. He is a member of the Royal Swedish Academy of Engineering Sciences, Academia Europaea and the Royal Spanish Academy of Engineering Science.


Uri Weiser

  • Uri Weiser (Technion IIT): Uri Weiser is a professor at the Electrical Engineering department of the Technion IIT. He is also active on the advisory boards of numerous startups. He earned his Ph.D in CS from the University of Utah, Salt Lake City.

Uri worked at Intel from 1988-2006 where he initiated and drove the definition of the first Pentium® processor, led the Intel's MMX™ technology, co-invented the Trace Cache, co-managed Intel’s new Design Center at Austin, Texas and formed an advanced media applications research activity. Uri was appointed Intel Fellow; he is an ACM Fellow, and Fellow of the IEEE. Prior to his career at Intel, Uri Weiser worked at the Israeli Department of Defense and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.


Pradip Bose

  • Pradip Bose (IBM): Pradip Bose received his B.Tech. (Hons.) degree in Electronics and Electrical Communication Engineering from I.I.T Kharagpur, India in 1977; his M.S. and Ph.D degrees in Electrical and Computer Engineering from University of Illinois, Urbana-Champaign in 1981 and 1983 respectively. Since 1983, Dr. Bose has been with IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA, where he currently manages the Department of Power- and Reliability-Aware Microarchitectures. He has been involved in the design and pre-silicon modeling of virtually all IBM POWER-series microprocessors, since the pioneering POWER1 (RS/6000) machine, which started as the Cheetah/America superscalar RISC project at IBM Research. From 1992-95, he was on assignment at IBM Austin, where he was the lead performance engineer in a high-end processor development project (POWER3).

During 1989-90, Dr. Bose was on a sabbatical assignment as a Visiting Professor at Indian Statistical Institute, India, where he worked on practical applications of knowledge-based systems. His current research interests are in high performance computers, power- and reliability aware microprocessor architectures, pre-silicon modeling and validation. Dr. Bose served as the Editor-in-Chief of IEEE Micro from 2003-2006. He is an IEEE Fellow. In 2008, he earned the title of IBM Master Inventor and is currently a member of IBM's Academy of Technology.


Jesus Labarta

  • Jesus Labarta (BSC/UPC): Jesus Labarta is full professor on Computer Architecture at the Technical University of Catalonia (UPC) since 1990. Since 1981 he has been lecturing on computer architecture, operating systems, computer networks and performance evaluation. His research interest has been centered on parallel computing, covering areas from multiprocessor architecture, memory hierarchy, parallelizing compilers, operating systems, parallelization of numerical kernels, performance analysis and prediction tools.

Since 1995 till 2004, he was director of CEPBA (European Center of Parallelism of Barcelona) where he was highly motivated by the promotion of parallel computing into industrial practice, and especially within SMEs. Since 2005 he is Director of the Computer Science Research Department within the Barcelona Supercomputing Center (BSC). He has been involved in research cooperation with many leading companies on HPC related topics. His major directions of current work relate to performance analysis tools, programming models and resource management. His team distributes the Open Source BSC tools (Paraver and Dimemas) and performs research on increasing the intelligence embedded in the performance analysis tools. He is involved in the development of the OmpSs programming model and its different implementations for SMPS, GPUs and clusters. He has been involved in Exascale activities such as IESP and EESI where he participated in the Runtime and Programming model sections of the respective Roadmaps.


Raymond Namyst

  • Raymond Namyst (University of Bordeaux): Raymond Namyst received his PhD from the University of Lille in 1997. He was lecturer at École Normale Supérieure de Lyon from 1998 to 2001. He became a full Professor at University of Bordeaux in September 2002. He is currently vice-chair of the Research and Training Department in Computer Science of the University of Bordeaux. He has been chair of the national scientific committee of the ANR “Numerical Simulation” program from 2011 to 2013. He has been Scientific Advisor at CEA/DAM (French Department of Energy) since 2007.

Raymond Namyst is the scientific leader of the “Runtime” Inria Research Group devoted to the design of high performance runtime systems for parallel architectures. His main research interests are parallel computing, scheduling on heterogeneous multiprocessor architectures (multicore, NUMA, accelerators), and communications over high-speed networks. He has supervised 20+ Ph.D students, and has written more than 80 papers on the design of efficient runtime systems. He has contributed to the development of many significant runtime systems (MPI, OpenMP) and most notably the StarPU software. He has been member of numerous conference program committees, including SC, PACT, EuroPar, Cluster, EuroMPI, CCGrid and HiPC. He was general co-chair of the Euro-Par 2011 international conference, and has served as a topic chair for SC'11 and Euro-Par'14.


Guri Sohi

  • Gurindar S. Sohi (University of Wisconsin-Madison): Guri Sohi has been a faculty member at the University of Wisconsin-Madison since 1985 where he currently a Vils Research Professor, the John P. Morgridge Professor and the E. David Cronon Professor of Computer Sciences. He was the Chair of the Computer Sciences Department from 2004 until 2008. Sohi's research has been in the design of high-performance microprocessors and computer systems. Results from his research can be found in almost every high-end microprocessor in the market today.

He received the 1999 ACM SIGARCH Maurice Wilkes award “for seminal contributions in the areas of high issue rate processors and instruction level parallelism” and the 2011 ACM/IEEE Eckert-Mauchly Award “for pioneering widely used micro-architectural techniques for instruction-level parallelism”. At the University of Wisconsin he was selected as a Vilas Associate in 1997, awarded the WARF Kellett Mid-Career Faculty Researcher award in 2000, and was selected as a WARF Named Professor in 2007. He is a Fellow of both the ACM and the IEEE and was elected to the National Academy of Engineering in 2009.


Keshav Pingali

  • Keshav Pingali (University of Texas at Austin): Keshav Pingali is a Professor in the Department of Computer Science at the University of Texas at Austin, and he holds the W.A.“Tex”Moncrief Chair of Computing in the Institute for Computational Engineering and Sciences (ICES) at UT Austin. He was on the faculty of the Department of Computer Science at Cornell University from 1986 to 2006, where he held the India Chair of Computer Science. Pingali's research has focused on programming languages and compiler technology for program understanding, restructuring, and optimization. His group is known for its contributions to memory-hierarchy optimization; some of these have been patented and are in use in industry compilers.

Pingali is a Fellow of the ACM, IEEE and AAAS. He was the co-Editor-in-chief of the ACM Transactions on Programming Languages and Systems, and currently serves on the editorial boards of the International Journal of Parallel Programming and Distributed Computing. He also served on the NSF CISE Advisory Committee (2009-2012).


Trevor Mudge

  • Trevor Mudge (University of Michigan, Ann Arbor): Trevor Mudge received the Ph.D. in Computer Science from the University of Illinois, Urbana. He is now a faculty at the University of Michigan, Ann Arbor, where he is the Bredt Family Professor of Computer Science and Engineering. He is author of numerous papers on computer architecture, programming languages, VLSI design, and computer vision. He has also chaired 51 theses in these areas. In 2014 he received the ACM/IEEE CS Eckert-Mauchly Award and the University of Illinois Distinguished Alumni Award. He is a Life Fellow of the IEEE, a member of the ACM, the IET, and the British Computer Society.


Dimitrios S. Nikolopoulos

  • Dimitrios S. Nikolopoulos (Queen's University of Belfast): Dimitrios S. Nikolopoulos is Professor and Head of the School of Electronics, Electrical Engineering and Computer Science, at Queen's University of Belfast. He holds the Chair in High Performance and Distributed Computing.

His research explores scalable computing systems for data-driven applications and new computing paradigms at the limits of performance, power and reliability. Dimitrios's accolades include the Royal Society Wolfson Research Merit Award, the NSF CAREER Award, the DOE CAREER Award, the IBM Faculty Award, the SFI-DEL Investigator Award. He is a Fellow of the British Computer Society.


Moinuddin Qureshi

  • Moinuddin Qureshi (Georgia Institute of Technology): Moinuddin Qureshi joined the faculty of the Georgia Institute of Technology as an Associate Professor in 2011. His research interests include computer architecture, scalable memory systems, fault tolerant computing, and analytical modeling of computer systems.

He worked as a research staff member at IBM T.J. Watson Research Center from 2007 to 2011. While at IBM, he contributed to the design of efficient caching algorithms for Power 7 processors. He was awarded the IBM outstanding technical achievement award for his studies on emerging memory technologies for server processors. He holds more than a dozen U.S. patents and has more than two-dozen publications in flagship architecture conferences. He received the Intel Early Faculty Career award and the NetApp Faculty Fellowship in 2012. He has served as a Program Committee member for several architecture conferences, including ISCA (2009, 2010, 2011, 2012), MICRO (2010, 2011), and HPCA (2015). He received his Ph.D. (2007) and M.S. (2003), both in Electrical Engineering from the University of Texas at Austin, and Bachelor of Electronics Engineering (2000) degree from University of Mumbai.


Chris Adeniyi-Jones

  • Chris Adeniyi-Jones (ARM): Chris Adeniyi-Jones is a Principal Engineer in ARM Research within the Software and Large-Scale Systems group. He holds a BSc in Physics with Electronics from the University of Manchester Institute of Science and Technology. His career started at Texas Instruments in the Design Automation Division where he worked on the development of in-house EDA tools and the deployment of commercial tools.

In 1994, he joined ARM in Cambridge initially developing EDA tools, then moving onto developing cycle-accurate processor models and tools for the creation of cycle-accurate processor models. He has also worked on ARM’s C/C++ compiler, implementing C/C++ language features and optimisations for code-size. Chris’s areas of research include many-core architectures, parallel programming models and dynamic binary instrumentation. He is ARM coordinator for European collaborative funded-projects such as the Mont-Blanc projects which are focussed on a European approach for energy-efficient high-performance computing.


Hans-Christian Hoppe

  • Hans Christian Hoppe (Intel) : Hans Christian Hoppe is a Principal Engineer with Intel and the director of the ExaCluster Lab at Research Center Jülich. He has a long track record in HPC R&D, with an emphasis on programming models and tools, application analysis and characterization, and path finding for future HPC platforms. His achievements include significant impact on the MPI message-passing standard, the first seamless & performant Grid infrastructure Unicore, pioneering use of virtualization in Grid/Cloud systems, and the Intel Cluster Tools line of SW products.

Between 2010 and 2012, he has led the Intel Visual Computing institute at Saarbrücken. With the ExaCluster Lab, Hans-Christian focuses on system architecture experiments using Intel many-core processors (like the European DEEP and DEEP-ER projects), and on scalable analysis tools and methods for important HPC and HPDA workloads and systems. He is Intel’s lead in the Horizon 2002 project NEXTGenIO, which investigates how to best leverage the emerging storage-class memory technology for Exascale systems.


Roger Espasa

  • Roger Espasa (Broadcom): Roger Espasa is currently Technical Director/Distinguished Engineer at Broadcom and leads a team designing a custom ARMv8/v7 processor on 28nm for the set-top box market. He got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture.

From 2002 to 2014 Roger worked at Intel as a Principal Engineer, leading the team on various x86 based projects: SIMD/vector unit and texture sampler on Knights Ferry (45nm), L2 cache, texture sampler on Knights Corner (22nm), and the out-of-order core on Knights Landing (14nm) and the Knights Hill (10nm) products. Roger has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.


Miquel Moreto

  • Miquel Moreto (BSC) is a senior researcher at BSC and an adjunct lecturer at UPC, Spain. He received the BS and MS degrees in mathematics and electrical engineering from UPC, and the PhD degree in 2010 in the Computer Architecture Department at the same university. He spent 15 months as a Fulbright postdoctoral fellow at the International Computer Science Institute (ICSI), Berkeley, USA.

His research interests include studying shared resources in multithreaded architectures and hardware-software co-design for future massively parallel systems. In 2013, he joined the BSC to work on the ERC-funded project RoMoL.


  • Marc Tremblay (Microsoft) is a Distinguished Engineer in the Silicon and Technology Group at Microsoft. His current role involves defining the strategic silicon roadmap for a broad range of products from devices to servers. His primary sphere of influence covers highly-integrated multi-core server SoCs, accelerators, as well as innovative multi-core SoCs for emerging devices. Marc has published numerous papers on throughput computing, multi-cores, scout threading, transactional memory, speculative multi-threading, Java computing, etc. He is the inventor of approximately 200 patents on those and other topics. Prior to joining Microsoft in 2009, Marc was the CTO of Microelectronics at Sun Microsystems, where he was a Sun Fellow and SVP. In his role as CTO he was responsible for the technical leadership of over 1200 engineers. Throughout his career, Marc has conceived, initiated, architected, led, defined and shipped a variety of microprocessors such as: superscalar RISC processors (UltraSPARC I/II), bytecode engines (picoJava), VLIW, media and Java-focused (MAJC) as well as the first processor to implement speculative multithreading and transactional memory (ROCK – first silicon). He was nominated as Innovator of the year by EDN. He received his Physics Engineering degree from Laval University in Canada and his M.S. and Ph.D degrees in Computer Sciences from UCLA.


  • Alper Buyuktosunoglu (IBM) received PhD degree in electrical and computer engineering from University of Rochester. Currently, he is a Research Staff Member in Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM p-series and z-series systems in the area of reliability and power-aware computer architectures. His research interests are in the area of high performance, power/reliability-aware computer architectures. He has over 70 pending/issued patents, has received several IBM-internal awards, has published over 70 papers, and has served on various conference technical program committees in this area. Dr. Buyuktosunoglu is an IBM Master Inventor and a senior member of the IEEE. He has been a member of the editorial board of Microelectronics Journal. He is currently serving on the editorial board of IEEE MICRO.


  • Lawrence Rauchwerger (Texas A&M University) is an Eppright Professor Computer Science at Texas A&M University and the co-Director of the Parasol Lab. He received an Engineer degree from the Polytechnic Institute Bucharest, a M.S. in Electrical Engineering from Stanford University and a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. He has held Visiting Faculty positions at the University of Illinois, Bell Labs, IBM T.J. Watson, and INRIA, Paris.

Rauchwerger's approach to auto-parallelization, thread-level speculation and parallel code development (STAPL) has influenced industrial products at corporations like IBM, Intel and Sun.

Rauchwerger is an IEEE Fellow and NSF CAREER, IBM and Intel faculty awards recipient. He has chaired various IEEE and ACM conferences.


  • Avi Mendelson (Technion IIT) is the head of the EE department in Engineering School, Kinnerent Collage and a visiting professor in the department of CS and department of EE. He has vast industrial experience, including 4 year as the manager the Academic relations of Microsoft R&D center in Israel, 10 years of experience as a senior computer Architect in Intel and more. While in Intel he was the chief architect of the CMP (multicore-on-chip) feature of the first two dual core processors Intel developed and led advance development activities of advanced heterogeneous systems.

Prof. Avi Mendelson research focuses at Computer architectures, Heterogeneous Systems, Operating systems, Power management, Reliability and advances new SW/HW interfaces.


  • Wen-mei W. Hwu (UIUC) is the Walter J. (“Jerry”) Sanders III-Advanced Micro Devices Endowed Chair in Electrical and Computer Engineering in the Coordinated Science Laboratory of the University of Illinois at Urbana-Champaign. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley, 1987.

His research interests are in the areas of architecture,implementation,software for high-performance computer systems, and parallel processing. He is a Principal Investigator(PI) for the petascale Blue Waters system, is co-director of the Intel and Microsoft funded Universal Parallel Computing Research Center (UPCRC), and PI for the world's first NVIDIA CUDA Center of Excellence. At the Illinois Coordinated Science Lab,he is the director of the OpenIMPACT project, which has delivered new compiler and computer architecture technologies to the computer industry since 1987. He also serves as the Soft Systems Theme leader of the MARCO/DARPA Gigascale Silicon Research Center (GSRC) and on the Executive Committees of both the GSRC and the MARCO/DARPA Center for Circuit and System Solutions (C2S2).

For his contributions to the areas of compiler optimization and computer architecture, he received the 1993 Eta Kappa Nu Outstanding Young Electrical Engineer Award, the 1994 Xerox Award for Faculty Research, the 1994 University Scholar Award of the University of Illinois, the 1997 Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the 1998 ACM SigArch Maurice Wilkes Award, the 1999 ACM Grace Murray Hopper Award, the 2001 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the 2002 ComputerWorld Honors Archive Medal. He is a fellow of IEEE and of the ACM.

speakers.txt · Last modified: 2016/03/16 18:26 by miquel
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