The following distinguished scientists have already accepted to speak at RoMoL 2016.
He earned his B.S. at Northeastern University and his M.S. and Ph.D. at Stanford University, all in electrical engineering. He has received a number of awards for his research and teaching, most notably the highest honor in his specialty computer architecture, the 1996 IEEE/ACM Eckert-Mauchly Award, “for important contributions to instruction level parallelism and superscalar processor design,” and the highest honor in computer science education, the 2000 ACM Karl V. Karlstrom Outstanding Educator Award. His research has spanned more than five decades, including WOS module (1966), HPS (starting in 1985), the two-level branch predictor (starting in 1991), SSMT (1999), ACMP (2007), Morphcore (2012), and the runahead buffer (2015).
He has co-authored (with his former PhD student Professor Sanjay Jeram Patel) “Introduction to Computing: from bits and gates to C and beyond” (McGraw-Hill 2000; 2e, 2004), a revolutionary approach to introducing serious students to computing. They are currently working on the 3rd edition.
Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work. He was the PI of the HTMT Project sponsored by NSF, DARPA, NSA, and NASA to explore advanced technologies and their implication for high-end computer system architectures. Other research projects included the DARPA DIVA PIM architecture project with USC-ISI, the Cray Cascade Petaflops architecture project sponsored by the DARPA HPCS Program, and the Gilgamesh high-density computing project at NASA JPL. Thomas Sterling is currently engaged in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding co-design for the development of future generation Exascale computing systems. ParalleX is currently the conceptual centerpiece of the XPRESS project as part of the DOE X-stack program and has been demonstrated in proof-of-concept in the HPX-5 runtime system software. Dr. Sterling is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS. He is also co-guest editor with Bill Gropp of the HPCwire Exascale Edition.
In 2003, Smith received the Seymour Cray Award from the IEEE Computer Society and was elected to the National Academy of Engineering. He received the Eckert-Mauchly Award in 1991 given jointly by IEEE and ACM and was elected a fellow of each organization in 1994. He was elected Fellow of the American Academy of Arts and Sciences in 2010. Smith attended the University of New Mexico, where he earned a BSEE degree, and the Massachusetts Institute of Technology, where he earned SM, EE, and Sc.D degrees.
Dr. Valero has been honored with several awards. Among them, the Eckert-Mauchly Award, Seymour Cray Award, Harry Goode Award, ACM Distinguished service, Euro-Par Achievement Award, the “King Jaime I” in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria, Zaragoza, Complutense de Madrid, Cantabria and Granada in Spain and by the University of Veracruz in Mexico. “Hall of the Fame” member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008). Prof. Valero is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow. He is a correspondent academic of the Royal Spanish Academy of Sciences, and member of the Royal Spanish Academy of Engineering, the Royal Academy of Science and Arts, the Academia Europea, and the Mexican Academy of Science.
He has been program chair or co-chair of the IEEE/ACM Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, the IEEE Parallel and Distributed Processing Symposium and ACM International Conference on Supercomputing. He is a member of the Royal Swedish Academy of Engineering Sciences, Academia Europaea and the Royal Spanish Academy of Engineering Science.
Uri worked at Intel from 1988-2006 where he initiated and drove the definition of the first Pentium® processor, led the Intel's MMX™ technology, co-invented the Trace Cache, co-managed Intel’s new Design Center at Austin, Texas and formed an advanced media applications research activity. Uri was appointed Intel Fellow; he is an ACM Fellow, and Fellow of the IEEE. Prior to his career at Intel, Uri Weiser worked at the Israeli Department of Defense and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.
During 1989-90, Dr. Bose was on a sabbatical assignment as a Visiting Professor at Indian Statistical Institute, India, where he worked on practical applications of knowledge-based systems. His current research interests are in high performance computers, power- and reliability aware microprocessor architectures, pre-silicon modeling and validation. Dr. Bose served as the Editor-in-Chief of IEEE Micro from 2003-2006. He is an IEEE Fellow. In 2008, he earned the title of IBM Master Inventor and is currently a member of IBM's Academy of Technology.
Since 1995 till 2004, he was director of CEPBA (European Center of Parallelism of Barcelona) where he was highly motivated by the promotion of parallel computing into industrial practice, and especially within SMEs. Since 2005 he is Director of the Computer Science Research Department within the Barcelona Supercomputing Center (BSC). He has been involved in research cooperation with many leading companies on HPC related topics. His major directions of current work relate to performance analysis tools, programming models and resource management. His team distributes the Open Source BSC tools (Paraver and Dimemas) and performs research on increasing the intelligence embedded in the performance analysis tools. He is involved in the development of the OmpSs programming model and its different implementations for SMPS, GPUs and clusters. He has been involved in Exascale activities such as IESP and EESI where he participated in the Runtime and Programming model sections of the respective Roadmaps.
Raymond Namyst is the scientific leader of the “Runtime” Inria Research Group devoted to the design of high performance runtime systems for parallel architectures. His main research interests are parallel computing, scheduling on heterogeneous multiprocessor architectures (multicore, NUMA, accelerators), and communications over high-speed networks. He has supervised 20+ Ph.D students, and has written more than 80 papers on the design of efficient runtime systems. He has contributed to the development of many significant runtime systems (MPI, OpenMP) and most notably the StarPU software. He has been member of numerous conference program committees, including SC, PACT, EuroPar, Cluster, EuroMPI, CCGrid and HiPC. He was general co-chair of the Euro-Par 2011 international conference, and has served as a topic chair for SC'11 and Euro-Par'14.
He received the 1999 ACM SIGARCH Maurice Wilkes award “for seminal contributions in the areas of high issue rate processors and instruction level parallelism” and the 2011 ACM/IEEE Eckert-Mauchly Award “for pioneering widely used micro-architectural techniques for instruction-level parallelism”. At the University of Wisconsin he was selected as a Vilas Associate in 1997, awarded the WARF Kellett Mid-Career Faculty Researcher award in 2000, and was selected as a WARF Named Professor in 2007. He is a Fellow of both the ACM and the IEEE and was elected to the National Academy of Engineering in 2009.
Pingali is a Fellow of the ACM, IEEE and AAAS. He was the co-Editor-in-chief of the ACM Transactions on Programming Languages and Systems, and currently serves on the editorial boards of the International Journal of Parallel Programming and Distributed Computing. He also served on the NSF CISE Advisory Committee (2009-2012).
His research explores scalable computing systems for data-driven applications and new computing paradigms at the limits of performance, power and reliability. Dimitrios's accolades include the Royal Society Wolfson Research Merit Award, the NSF CAREER Award, the DOE CAREER Award, the IBM Faculty Award, the SFI-DEL Investigator Award. He is a Fellow of the British Computer Society.
He worked as a research staff member at IBM T.J. Watson Research Center from 2007 to 2011. While at IBM, he contributed to the design of efficient caching algorithms for Power 7 processors. He was awarded the IBM outstanding technical achievement award for his studies on emerging memory technologies for server processors. He holds more than a dozen U.S. patents and has more than two-dozen publications in flagship architecture conferences. He received the Intel Early Faculty Career award and the NetApp Faculty Fellowship in 2012. He has served as a Program Committee member for several architecture conferences, including ISCA (2009, 2010, 2011, 2012), MICRO (2010, 2011), and HPCA (2015). He received his Ph.D. (2007) and M.S. (2003), both in Electrical Engineering from the University of Texas at Austin, and Bachelor of Electronics Engineering (2000) degree from University of Mumbai.
In 1994, he joined ARM in Cambridge initially developing EDA tools, then moving onto developing cycle-accurate processor models and tools for the creation of cycle-accurate processor models. He has also worked on ARM’s C/C++ compiler, implementing C/C++ language features and optimisations for code-size. Chris’s areas of research include many-core architectures, parallel programming models and dynamic binary instrumentation. He is ARM coordinator for European collaborative funded-projects such as the Mont-Blanc projects which are focussed on a European approach for energy-efficient high-performance computing.
Between 2010 and 2012, he has led the Intel Visual Computing institute at Saarbrücken. With the ExaCluster Lab, Hans-Christian focuses on system architecture experiments using Intel many-core processors (like the European DEEP and DEEP-ER projects), and on scalable analysis tools and methods for important HPC and HPDA workloads and systems. He is Intel’s lead in the Horizon 2002 project NEXTGenIO, which investigates how to best leverage the emerging storage-class memory technology for Exascale systems.
From 2002 to 2014 Roger worked at Intel as a Principal Engineer, leading the team on various x86 based projects: SIMD/vector unit and texture sampler on Knights Ferry (45nm), L2 cache, texture sampler on Knights Corner (22nm), and the out-of-order core on Knights Landing (14nm) and the Knights Hill (10nm) products. Roger has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.
His research interests include studying shared resources in multithreaded architectures and hardware-software co-design for future massively parallel systems. In 2013, he joined the BSC to work on the ERC-funded project RoMoL.
Rauchwerger's approach to auto-parallelization, thread-level speculation and parallel code development (STAPL) has influenced industrial products at corporations like IBM, Intel and Sun.
Rauchwerger is an IEEE Fellow and NSF CAREER, IBM and Intel faculty awards recipient. He has chaired various IEEE and ACM conferences.
Prof. Avi Mendelson research focuses at Computer architectures, Heterogeneous Systems, Operating systems, Power management, Reliability and advances new SW/HW interfaces.
His research interests are in the areas of architecture,implementation,software for high-performance computer systems, and parallel processing. He is a Principal Investigator(PI) for the petascale Blue Waters system, is co-director of the Intel and Microsoft funded Universal Parallel Computing Research Center (UPCRC), and PI for the world's first NVIDIA CUDA Center of Excellence. At the Illinois Coordinated Science Lab,he is the director of the OpenIMPACT project, which has delivered new compiler and computer architecture technologies to the computer industry since 1987. He also serves as the Soft Systems Theme leader of the MARCO/DARPA Gigascale Silicon Research Center (GSRC) and on the Executive Committees of both the GSRC and the MARCO/DARPA Center for Circuit and System Solutions (C2S2).
For his contributions to the areas of compiler optimization and computer architecture, he received the 1993 Eta Kappa Nu Outstanding Young Electrical Engineer Award, the 1994 Xerox Award for Faculty Research, the 1994 University Scholar Award of the University of Illinois, the 1997 Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the 1998 ACM SigArch Maurice Wilkes Award, the 1999 ACM Grace Murray Hopper Award, the 2001 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the 2002 ComputerWorld Honors Archive Medal. He is a fellow of IEEE and of the ACM.